Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel

US6544824B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Lap Chan · San Francisco, US
• Elgin Quek · Singapore, SG
• Ravi Sundaresan · San Jose, US
• Yang Pan · Singapore, SG
• James Lee Yong Meng · Singapore, SG
• Ying Keung · Hong Kong, CN

Key dates

• Filing date: Jan 3, 2002
• Grant date: Apr 8, 2003
• Expiry date: Jan 3, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/025

Abstract

A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.