Method for forming junction on insulator (JOI) structure
US6544874B2 · kind B2 · utility
22Cited by
10References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.