Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing
US6720234B2 · kind B2 · utility
2Cited by
2References
28Claims
0Family size
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Key dates
| Filing date | Feb 14, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Feb 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.