Multiple gate transistor employing monocrystalline silicon walls

US6753216B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Leo Mathew · Austin, US
• Bich-Yen Nguyen · Austin, US
• Daniel T. Pham · Clifton Park, US
• Anne Vandooren · Mazy, BE

Key dates

• Filing date: Oct 31, 2002
• Grant date: Jun 22, 2004
• Expiry date: Oct 31, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6758

Abstract

A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).