Method for reducing gate line deformation and reducing gate line widths in semiconductor devices

US6764947B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Darin A. Chan · Campbell, US
• Douglas J. Bonser · Irving, US
• Marina V. Plat · San Jose, US
• Marilyn I. Wright · Austin, US
• Chih-Yuh Yang · San Jose, US
• Lu You · Santa Clara, US
• Scott A. Bell · San Jose, US
• Philip A. Fisher · Foster City, US

Key dates

• Filing date: Feb 14, 2003
• Grant date: Jul 20, 2004
• Expiry date: Feb 14, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.