Simultaneous native oxide removal and metal neutral deposition method

US6784105B1 · kind B1 · utility

Assignees

• Infineon Technologies North America Corp. · US
• International Business Machines Corporation · US
• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Chih-Chao Yang · Glenmont, US
• Yun-Yu Wang · Poughquag, US
• Larry Clevenger · Lagrangeville, US
• Andrew H. Simon · Fishkill, US
• Stephen E. Greco · Lagrangeville, US
• Kaushik Chanda · Fishkill, US
• Terry A. Spooner · Clifton Park, US
• Andy Cowley · Wappingers Falls, US
• Sunfei Fang · Lagrangeville, US

Key dates

• Filing date: Apr 9, 2003
• Grant date: Aug 31, 2004
• Expiry date: Apr 9, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76865
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.