Method of determining charge loss activation energy of a memory array
US6813752B1 · kind B1 · utility
3Cited by
9References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 26, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Nov 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.