Multi-dice chip scale semiconductor components and wafer level methods of fabrication

US6841883B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Warren M. Farnworth · Nampa, US
• Alan G. Wood · Boise, US
• William M. Hiatt · Eagle, US
• James M. Wark · Boise, US
• David R. Hembree · Boise, US
• Kyle K. Kirby · Eagle, US
• Pete Benson · Boise, US

Key dates

• Filing date: Mar 31, 2003
• Grant date: Jan 11, 2005
• Expiry date: May 7, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19041
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.