Timing calibration pattern for SLDRAM
US6889357B1 · kind B1 · utility
58Cited by
12References
94Claims
0Family size
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Key dates
| Filing date | May 10, 2000 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.