System and method for product yield prediction

US6901564B2 · kind B2 · utility

Assignee

• PDF SOLUTIONS, INC. · US

Inventors

• Brian E. Stine · Los Altos Hills, US
• Christopher Hess · Belmont, US
• John Kibarian · Los Altos Hills, US
• Kimon Michaels · Monte Sereno, US
• Joseph C. Davis · Allen, US
• Purnendu K. Mozumder · Dallas, US
• Sherry Lee · San Jose, US
• Larg Weiland · Hollister, US
• Dennis Ciplickas · San Jose, US
• David Stashower · Los Gatos, US

Key dates

• Filing date: Jul 18, 2002
• Grant date: May 31, 2005
• Expiry date: Dec 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.