Wafer level MEMS packaging

US6953985B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Jong-Kai Lin · Chandler, US
• William H. Lytle · Chandler, US
• Owen R. Fay · Meridian, US
• Steven Markgraf · Plymouth, US
• Henry G. Hughes · Scottsdale, US
• Craig Amrine · Tempe, US
• Ananda De Silva · Chandler, US

Key dates

• Filing date: Jun 12, 2002
• Grant date: Oct 11, 2005
• Expiry date: Aug 7, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.