Method of growing as a channel region to reduce source/drain junction capacitance
US6955969B2 · kind B2 · utility
88Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Sep 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.