Memory cell structure having nitride layer with reduced charge loss and method for fabricating same

US6992370B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• George Jonathan Kluth · Sunnyvale, US
• Robert Clark-Phelps · Northborough, US
• Joong S. Jeon · Seongnam-si, KR
• Huicai Zhong · San Jose, US
• Arvind Halliyal · Cupertino, US
• Mark T. Ramsbey · Sunnyvale, US
• Robert B. Ogle · San Jose, US
• Kuo-Tung Chang · Saratoga, US
• Wenmei Li · San Jose, US

Key dates

• Filing date: Sep 4, 2003
• Grant date: Jan 31, 2006
• Expiry date: Sep 4, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.