Composite stress spacer
US7256084B2 · kind B2 · utility
12Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jun 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.