Stacked die in die BGA package
US7332819B2 · kind B2 · utility
7Cited by
52References
67Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Feb 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and stacked die assemblies, are provided which have at least two semiconductor dies disposed on a substrate in a stacked arrangement, the first and second dies having first surfaces having bond pads, the second die having a second surface with a recessed edge portion along a perimeter of that die, and the recessed edge portion having a height sufficient for clearance of bonding elements extending from the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.