Stacked die in die BGA package
US7332820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted on a substrate and a second die mounted on the first die. In one embodiment, the second die has a recessed edge along the perimeter of the bottom surface to provide clearance for a bonding element extending from bond pads on the first die to pads on the substrate, thus eliminating the need for a spacer between the two dies. In another embodiment, the second die is at least partially disposed within a recess in the upper surface of the first die. In another embodiment, an adhesive element is disposed within a recess in the bottom surface of the first die for attaching the first die to the substrate. In yet another embodiment, the first die is at least partially disposed within a recess within the bottom surface of the second die. The stacked die assemblies can be encapsulated to form semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.