Memory cell having enhanced high-K dielectric
US7365389B1 · kind B1 · utility
76Cited by
23References
11Claims
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Key dates
| Filing date | Dec 10, 2004 |
| Grant date | Apr 29, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.