Methods and structures for protecting one area while processing another area on a chip

US7497959B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Deok-kee Kim · Mount Kisco, US
• Kenneth T. Settlemyer, Jr. · Poughquag, US
• Kangguo Cheng · Schenectady, US
• Ramachandra Divakaruni · Ossining, US
• Carl Radens · Lagrangeville, US
• Dirk Pfeiffer · Dobbs Ferry, US
• Timothy J. Dalton · Ridgefield, US
• Katherina Babich · Chappaqua, US
• Arpan Mahorowala · West Linn, US
• Harald Okorn-Schmidt · Putnam Valley, US

Key dates

• Filing date: May 11, 2004
• Grant date: Mar 3, 2009
• Expiry date: Apr 5, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G03F7/11
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.