Trench-gate field effect transistors and methods of forming the same
US7504303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Aug 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a shielded gate field effect transistor includes the following steps. Trenches extending into a silicon region are formed using a mask that includes a protective layer. A shield dielectric layer lining sidewalls and bottom of each trench is formed. A shield electrode is formed in a bottom portion of each trench. Protective spacers are formed along upper sidewalls of each trench. An inter-electrode dielectric is formed over the shield electrode. The protective spacers and the protective layer of the mask prevent formation of inter-electrode dielectric along the upper sidewalls of each trench and over mesa surfaces adjacent each trench. A gate electrode is formed in each trench over the inter-electrode dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.