Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

US7575975B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Voon-Yew Thean · Fishkill, US
• Jian Chen · Austin, US
• Bich-Yen Nguyen · Austin, US
• Mariam Sadaka · Austin, US
• Da Zhang · New Taipei, TW

Key dates

• Filing date: Oct 31, 2005
• Grant date: Aug 18, 2009
• Expiry date: Jul 25, 2026

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/938

Abstract

Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.