Advanced multilayer dielectric cap with improved mechanical and electrical properties
US7737052B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 5, 2008 |
| Grant date | Jun 15, 2010 |
| Priority date | — |
| Expiry date | Oct 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02348
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.