Self-aligned contact
US7888252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2009 |
| Grant date | Feb 15, 2011 |
| Priority date | — |
| Expiry date | Apr 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.