Memory cell system with charge trap

US8143661B2 · kind B2 · utility

Assignees

• Spansion LLC. · US
• Advanced Micro Devices, Inc. · US

Inventors

• Shenqing Fang · Fremont, US
• Rinji Sugino · San Jose, US
• Jayendra D. Bhakta · Sunnyvale, US
• Takashi Orimoto · Sunnyvale, US
• Hiroyuki Nansei · Aizuwakamatsu, JP
• Yukio Hayakawa · Tochigi, JP
• Takayuki Maruyama · Tokyo, JP
• Hidehiko Shiraiwa · San Jose, US
• Kuo-Tung Chang · Saratoga, US
• Lei Xue · 红钢城街道, CN
• Meng Ding · Beaumont, US
• Amol Joshi · Sunnyvale, US
• Youseok Suh · Cupertino, US
• Harpreet Sachar · Milpitas, US

Key dates

• Filing date: Oct 10, 2006
• Grant date: Mar 27, 2012
• Expiry date: Sep 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.