Voltage-based memory size scaling in a data processing system

US8156357B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Shayan Zhang · Cedar Park, US
• James D. Burnett · Austin, US
• Prashant U. Kenkare · Austin, US
• Hema Ramamurthy · Austin, US
• Andrew C. Russell · Austin, US
• Michael D. Snyder · Cedar Park, US

Key dates

• Filing date: Jan 27, 2009
• Grant date: Apr 10, 2012
• Expiry date: Jul 13, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.