Structure with isotropic silicon recess profile in nanoscale dimensions
US8232171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2009 |
| Grant date | Jul 31, 2012 |
| Priority date | — |
| Expiry date | May 28, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.