Interconnect structure for integrated circuits having enhanced electromigration resistance

US8232646B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Griselda Bonilla · Hopewell Junction, US
• Kaushik Chanda · Fishkill, US
• Ronald G. Filippi · Wappingers Falls, US
• Stephan Grunow · Poughkeepsie, US
• Chao-Kun Hu · Somers, US
• Naftali E. Lustig · Ossining, US
• Andrew H. Simon · Fishkill, US
• Ping-Chuan Wang · Hopewell Junction, US

Key dates

• Filing date: Jan 21, 2010
• Grant date: Jul 31, 2012
• Expiry date: Feb 5, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.