Patent · US Active

Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

US8247281B2 · kind B2 · utility

9Cited by

2References

18Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Klaus Hempel · Dresden, DE
Patrick Press · Dresden, DE
Vivien Schroeder · Radeberg, DE
Berthold Reimer · Dresden, DE
Johannes Groschopf · Radebeul, DE

Key dates

Filing date	Jun 24, 2010
Grant date	Aug 21, 2012
Priority date	—
Expiry date	Oct 18, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0167
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.