Method to improve source/drain parasitics in vertical devices
US8258035B2 · kind B2 · utility
3Cited by
11References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2007 |
| Grant date | Sep 4, 2012 |
| Priority date | — |
| Expiry date | Apr 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.