High performance CMOS circuits, and methods for fabricating same

US8383483B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John C. Arnold · North Chatham, US
• Glenn A. Biery · Poughkeepsie, US
• Alessandro C. Callegari · Yorktown Heights, US
• Tze-Chiang Chen · Yorktown Heights, US
• Michael P. Chudzik · Beacon, US
• Bruce B. Doris · Brewster, US
• Michael A. Gribelyuk · Stamford, US
• Young-Hee Kim · Potsdam, US
• Barry P. Linder · Hastings-on-Hudson, US
• Vijay Narayanan · New York, US
• Joseph S. Newbury · Dobbs Ferry, US
• Vamsi K. Paruchuri · New York, US
• Michelle L. Steen · Danbury, US

Key dates

• Filing date: Aug 14, 2009
• Grant date: Feb 26, 2013
• Expiry date: Aug 3, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.