Semiconductor devices fabricated by doped material layer as dopant source
US8394710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Dec 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.