Local interconnect structure self-aligned to gate structure
US8455932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Sep 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.