Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability

US8465657B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kaushik Chanda · Fishkill, US
• James J. Demarest · Rensselaer, US
• Ronald G. Filippi · Wappingers Falls, US
• Roy Iggulden · Newburgh, US
• Edward W. Kiewara · Verbank, US
• Ping-Chuan Wang · Hopewell Junction, US
• Yun-Yu Wang · Poughquag, US

Key dates

• Filing date: Aug 3, 2007
• Grant date: Jun 18, 2013
• Expiry date: Nov 6, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T29/49204
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.