Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices
US8524592B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Aug 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.