Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation
US8541274B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2012 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Sep 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.