Reduction of forming voltage in semiconductor devices
US8551809B2 · kind B2 · utility
9Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Apr 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device and methods of manufacturing the same has one electrode with a higher work function and a second electrode with a lower work function. The nonvolatile memory device further comprises one or more resistive random access memory (RRAM) cells. The RRAM cells comprise a semiconductor layer with a bandgap of at least four electron volts and a barrier layer between the semiconductor layer and one of the electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.