Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation

US8580634B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ruilong Xie · Niskayuna, US
• Xiuyu Cai · San Diego, US
• Kangguo Cheng · Schenectady, US
• Ali Khakifirooz · Los Altos, US

Key dates

• Filing date: Sep 11, 2012
• Grant date: Nov 12, 2013
• Expiry date: Sep 11, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.