Threshold voltage adjustment in a Fin transistor by corner implantation

US8580643B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Tim Baldauf · Dresden, DE
• Andy Wei · Queensbury, US
• Tom Herrmann · Dresden, DE
• Stefan Flachowsky · Dresden, DE
• Ralf Illgen · Dresden, DE

Key dates

• Filing date: Aug 24, 2011
• Grant date: Nov 12, 2013
• Expiry date: Oct 19, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.