Stacked via structure for metal fuse applications
US8633707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2011 |
| Grant date | Jan 21, 2014 |
| Priority date | — |
| Expiry date | Apr 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.