Integrating transistors with different poly-silicon heights on the same die
US8652907B2 · kind B2 · utility
6Cited by
1References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Jun 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.