MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture
US8652963B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Feb 18, 2014 |
| Priority date | — |
| Expiry date | Nov 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.