Self-aligned multiple gate transistor formed on a bulk substrate

US8679924B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andy Wei · Queensbury, US
• Vivien Schroeder · Radeberg, DE
• Thilo Scheiper · Dresden, DE
• Thomas Werner · Radebeul, DE
• Johannes Groschopf · Radebeul, DE

Key dates

• Filing date: Jan 31, 2011
• Grant date: Mar 25, 2014
• Expiry date: Oct 9, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.