Electronic anti-fuse
US8736020B2 · kind B2 · utility
7Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | May 27, 2014 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.