Methods of increasing space for contact elements by using a sacrificial liner and the resulting device
US8841711B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.