Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods

US8860123B1 · kind B1 · utility

Assignees

• STMICROELECTRONICS, INC. · US
• International Business Machines Corporation · US

Inventors

• Prasanna Khare · Schenectady, US
• Stephane Allegret-Maret · Grenoble, FR
• Nicolas Loubet · Guilderland, US
• Qing Liu · Guilderland, US
• Hemanth Jagannathan · Niskayuna, US
• Lisa F. Edge · Watervliet, US
• Kangguo Cheng · Schenectady, US
• Bruce B. Doris · Brewster, US

Key dates

• Filing date: Mar 28, 2013
• Grant date: Oct 14, 2014
• Expiry date: Mar 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.