Methods related to power semiconductor devices with thick bottom oxide layers
US8936985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2012 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Mar 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.