Strain engineering in three-dimensional transistors based on strained isolation material

US8941187B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Tim Baldauf · Dresden, DE
• Andy Wei · Queensbury, US
• Tom Herrmann · Dresden, DE
• Stefan Flachowsky · Dresden, DE
• Ralf Illgen · Dresden, DE

Key dates

• Filing date: Jan 13, 2012
• Grant date: Jan 27, 2015
• Expiry date: Mar 4, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/795

Abstract

In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.