Reduction of forming voltage in semiconductor devices
US8963117B2 · kind B2 · utility
3Cited by
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17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.