Shielded gate trench MOS with improved source pickup layout
US8994101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Nov 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.