Method for forming a Ge on III/V-on-insulator structure
US9018678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Aug 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6741
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.