Deeply depleted MOS transistors having a screening layer and methods thereof

US9041126B2 · kind B2 · utility

Assignee

• Mie Fujitsu Semiconductor Limited · JP

Inventors

• Thomas Hoffmann · Santa Cruz, US
• Lucian Shifren · San Jose, US
• Scott E. Thompson · Gainesville, US
• Pushkar Ranade · Los Gatos, US
• Jing Wang · Broomfield, US
• Paul E. Gregory · Palo Alto, US
• Sachin R. Sonkusale · Los Gatos, US
• Lance Scudder · Sunnyvale, US
• Dalong Zhao · San Jose, US
• Teymur Bakhishev · San Jose, US
• Yujie Liu · Beijing, CN
• Lingquan Wang · Irvine, US
• Weimin Zhang · San Jose, US
• Sameer Pradhan · Campbell, US
• Michael Duane · Austin, US
• Sung Hwan Kim · Seojong-myeon, KR

Key dates

• Filing date: Sep 5, 2013
• Grant date: May 26, 2015
• Expiry date: Sep 5, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/608

Abstract

A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.